1. Field of the Invention
The present invention generally relates to test systems for integrated circuits and more particularly to a built in self test circuit for a variable impedance system.
2. Description of the Related Art
In electrical systems, output drivers are used to drive input/output (I/O) devices or similar loads. Each output driver is set up with a certain voltage/impedance that matches the strength of the transmission line and I/O device being driven by that specific driver. Thus, I/O devices with a low drive strength would need an output driver with a high impedance, and high strength I/O devices require a low impedance driver. Since some output drivers have only one impedance rating, an output driver driving a load other than the one it is designed for would result in too much or too little of the strength needed.
In addition, output driver impedance variations as a result of supply voltage, temperature, and process variations may be as high as 100% of the desired impedance. Consequently, such a system would suffer in performance from factors such as slow downs of a high performance system and/or dissipation of dc power. The mismatch between the SRAM output driver and the characteristic line impedance of the system is very undesirable in high performance and small signal applications, such as cache to processor I/O interfaces. Furthermore, if a separate part was designed for the many different load strengths across different systems, the costs may become expensive.
One solution to overcome using several single impedance output drivers is to use one output driver with a variable resistor external to the output driver (discussed in greater detail below with respect to FIG. 1). With such a driver, a user may change the external resistor of the driver to reflect the voltage/impedance needed to drive a load.
The driver needs to have an impedance that matches the transmission line being driven. The overall impedance of the driver circuit is obtained through the circuit""s xe2x80x9ccountxe2x80x9d, as discussed in greater detail below. However, as the impedance tolerance of such drivers varies, the system""s performance degrades and testing such drivers has proved a difficult proposition. Accordingly, a need has developed in the art for a programmable impedance output driver circuit that will not only provide a variable impedance in its circuitry, but will also be easily tested for defects.
Another advantage of variable impedance drivers is the ability to meet different impedance requirements with the same chip. For example, the same chip can provide a 35-xcexa9 driver for one application and a 70-xcexa9 driver for another application. The only difference between the two applications is the value of the external variable resistor.
In view of the foregoing, it is an object of the invention to provide a programmable impedance driver that includes two sets of impedance devices, two primary counters operatively connected to respective ones of the sets of the impedance devices (the primary counters selectively activate individual ones of the impedance devices to vary an overall impedance of the driver), and two test counters. The test counters verify an operation of the primary counters during manufacturing testing of the driver.
The invention also includes two comparators receiving signals from respective ones of the primary counters and respective ones of the test counters. These comparators determine if respective pairs of the primary counters and the test counters have identical counts. A test output pin is connected to the comparators and outputs a signal indicating a functionality of the primary counters.
The sets of impedance devices includes p-type field effect transistors (PFET) and n-type field effect transistors (NFET). Similarly, the primary counters include a PFET primary counter and an NFET primary counter and the test counters include a PFET test counter and an NFET test counter.
The invention also includes test control logic connected to the PFET primary counter, the NFET primary counter, the PFET test counter, and the NFET test counter. The test control logic resets the PFET primary counter and the PFET test counter to all zero at the start of testing and resets the NFET primary counter and the NFET test counter to all ones at the start of testing. During testing, the PFET primary counter and the PFET test counter are initially incremented, and the NFET primary counter and the NFET test counter are initially decremented.
Thus, the invention includes two primary counters and two test counters. The primary counters selectively activate individual ones of the impedance devices to vary an overall impedance of the driver during normal use and the test counters verify the counting operation of the primary counters during manufacturing testing of the driver. Therefore, the built-in self-test (BIST) aspect of the invention easily detects if one of the counters will become stuck during normal usage. The invention achieves greater than 90% testability of variable impedance systems found in high-speed ICs. The need for on-chip circuitry to test the variable impedance circuit arises from the inability to test this circuit during manufacturing. The invention achieves a high degree of testability without compromising accuracy of the impedance circuit and uses an existing state machine (e.g., JTAG) to accomplish the testing. Furthermore, the added logic to accomplish a high degree of testability is kept to a minimum and is very easily integratable into the existing variable impedance system.